I am able to simulate my cpu with no errors and received the waveforms I expected. So I went to run the synthesis and I received my foreplaning, i/o planning, and etc. However it did not produce a schematic.
There are many warnings after synthesis:
Here is my Verilog code:
`timescale 1ns / 1ps
module CPU( input clk ); wire [31:0] Mux4_PC; wire [31:0] PC_Adder_InstMem; wire [31:0] Adder_Mux4; wire [31:0] Instruction; wire [31:0] qa_Mux; wire [31:0] qb_ALU; wire [31:0] mux_ALU; wire [31:0] ALU_d; wire [1:0] pcsrc; wire [3:0] aluc; wire shift; wire wreg; wire zOut; PC PC(clk, Mux4_PC, PC_Adder_InstMem); InstMem InstMem(PC_Adder_InstMem, Instruction); PCadder PCadder(PC_Adder_InstMem, Adder_Mux4); ControlUnit ControlUnit(Instruction[31:26], Instruction[5:0],aluc, pcsrc, wreg, shift); regfile regfile(.d(ALU_d), .rna(Instruction[25:21]), .rnb(Instruction[20:16]), .wn(Instruction[15:11]), .we(wreg), .clk(clk), .clrn(_), .qa(qa_Mux), .qb(qb_ALU)); shiftMux shiftMux(shift, qa_Mux, Instruction[10:6], mux_ALU); ALU ALU(.a(mux_ALU), .b(qb_ALU), .aluc(aluc), .r(ALU_d), .zOut(zOut)); input4Mux input4Mux(.in0(Adder_Mux4), .in1(_), .in2(_), .in3(_), .pcsrc(pcsrc), .out(Mux4_PC));
endmodule
module ControlUnit( input [5:0] op, func, output reg [3:0] aluc, output reg [1:0] pcsrc, output reg wreg, output reg shift ); always @(op, func) begin case(op) 0: // R-FORMAT case(func) 0: // SLL begin aluc <= 4'b0011; pcsrc <= 2'b00; wreg <= 1; shift <= 1; end 34: // SUB begin aluc <= 4'b0100; pcsrc <= 2'b00; wreg <= 1; shift <= 0; end 37: // OR begin aluc <= 4'b0101; pcsrc <= 2'b00; wreg <= 1; shift <= 0; end endcase endcase end
endmodule
module ALU( input [31:0] a, b, input [3:0] aluc, output reg [31:0] r, output reg zOut ); always @(aluc, a, b) begin case(aluc) 0: // ADD r <= a + b; 3: // SLL r <= b << a; 4: // SUB r <= a - b; 5: // OR r <= a | b; endcase end
endmodule
module regfile( input [31:0] d, // data of write port input [4:0] rna, // reg # of read port A input [4:0] rnb, // reg # of read port B input [4:0] wn, // reg # of write port input we, // write enable input clk, clrn, output [31:0] qa, qb // read ports A and B ); reg [31:0] register [1:31]; // 31 32-bit registers assign qa = (rna == 0)? 0 : register[rna]; // read port A, qa = 0 if rna==0 is true, qa = register[rna] if rna==0 is false assign qb = (rnb == 0)? 0 : register[rnb]; // read port B integer i; initial begin register[1] = 32'ha00000aa; register[2] = 32'h10000011; register[3] = 32'h20000022; register[4] = 32'h30000033; register[5] = 32'h40000044; register[6] = 32'h50000055; register[7] = 32'h60000066; register[8] = 32'h70000077; register[9] = 32'h80000088; register[10] = 32'h90000099; end always @(posedge clk or negedge clrn) // write port begin if (!clrn) begin for (i = 1; i < 32; i = i + 1) begin register[i] <= 0; // reset end end else if ((wn != 0) && we) // not reg[0] & enabled begin register[wn] <= d; // write d to reg[wn] end end
endmodule
module InstMem( input [31:0]a, output reg [31:0] do ); reg [7:0] instruc [1:12]; initial begin instruc[1] = 8'h01; //sub $t0, $t1, $a0 instruc[2] = 8'h24; instruc[3] = 8'h40; instruc[4] = 8'h22; instruc[5] = 8'h01; //or $a2, $t2, $t1 instruc[6] = 8'h49; instruc[7] = 8'h30; instruc[8] = 8'h25; instruc[9] = 8'h00; //sll $t0, $a1, 15 instruc[10] = 8'h05; instruc[11] = 8'h43; instruc[12] = 8'hc0; end always @* begin do [31:24] <= instruc[a+1]; do [23:16] <= instruc[a+2]; do [15:8] <= instruc[a+3]; do [7:0] <= instruc[a+4]; end
endmodule
module PC( input clk, input [31:0] in, output reg [31:0] out ); initial begin out <= 32'h00000000; end always @(posedge clk) begin out <= in; end
endmodule
module PCadder( input [31:0] PCin, output reg [31:0] PCadd ); always @(PCin) begin PCadd <= PCin + 32'h00000004; end
endmodule
module shiftMux( input shift, input [31:0] qa, input [4:0] sa, output reg [31:0] shiftMuxOut ); always @(qa,sa,shift) begin if (shift == 1) begin shiftMuxOut [31:5] <= 27'b0; shiftMuxOut [4:0] <= sa; end else begin shiftMuxOut <= qa; end end
endmodule
module input4Mux( input [31:0] in0, in1, in2, in3, input [1:0] pcsrc, output reg [31:0] out ); always @(in0, in1, in2, in3, pcsrc) begin case(pcsrc) 0: out <= in0; 1: out <= in1; 2: out <= in2; 3: out <= in3; endcase end
endmoduleI am able to get a RTL Analysis Schematic however I really need the Synthesis Schematic. Is something causing it to become unsynthesizable?
1 Answer
Warning messages explained:
The entire design is being optimized/logic-trimmed by synthesis because the top level module (CPU) has no outputs, and almost no inputs.
The internal variables in the CPU module are hanging in space (not connected to the top level module outputs) therefore synthesis removes them.The tool is indicating that is is performing logic trimming in the warnings:
'... has no load'
'... is unconnected'
'... unused and will be removed'.With the entire design optimized away, there is nothing which could be used to create a schematic.
To fix this, add outputs to the top level and connect the internal nodes to the top level.
The design also has no inputs except clk.
Also add the missing inputs.
Like this:
module CPU( input clk, // inputs input wire [3:0] aluc, // more inputs ... // outputs output wire [31:0] ALU_d ); // local variables wire [31:0] Mux4_PC; wire [31:0] PC_Adder_InstMem; wire [31:0] Adder_Mux4; wire [31:0] Instruction; wire [31:0] qa_Mux; wire [31:0] qb_ALU; wire [31:0] mux_ALU; // wire [31:0] ALU_d; wire [1:0] pcsrc; // wire [3:0] aluc; wire shift; wire wreg; wire zOut;The latch inference message is a separate issue which should be addressed
(unless the design intent is to infer latches).
This is a common often asked/answered issue.
Here is an answer which explains:
What is inferred latch and how it is created when it is missing else statement in if condition. Can anybody explain briefly?
In your code the case statementsdefault :statements are missing.The message about parallel synthesis is the tool indicating it will not optimize further because the design is already optimized away.
